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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
(R)
Comlinear CLC1050, CLC2050, CLC4050
FEATURES n Unity gain stable n 100dB voltage gain n 550kHz unity gain bandwidth n 0.5mA supply current n 20nA input bias current n 2mV input offset voltage n 3V to 36V single supply voltage range n 1.5V to 18V dual supply voltage range n Input common mode voltage range includes ground n 0V to VS-1.5V output voltage swing n CLC2050: improved replacement for industry standard LM358 n CLC4050: Improved replacement for industry standard LM324 n CLC1050: Pb-free SOT23-5 n CLC2050: Pb-free SOIC-8 n CLC4050: Pb-free SOIC-14 APPLICATIONS n Battery Charger n Active Filters n Transducer amplifiers n General purpose controllers n General purpose instruments
Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
General Description
The COMLINEAR CLC1050 (single), CLC2050 (dual), and CLC4050 (quad) are voltage feedback amplifiers that are internally frequency compensated to provide unity gain stability. At unity gain (G=1), these amplifiers offer 550kHz of bandwidth. They consume only 0.5mA of supply current over the entire power supply operating range. The CLC1050, CLC2050, and CLC4050 are specifically designed to operate from single or dual supply voltages. The COMLINEAR CLC1050, CLC2050, and CLC4050 offer a common mode voltage range that includes ground and a wide output voltage swing. The combination of low-power, high supply voltage range, and low supply current make these amplifiers well suited for many general purpose applications and as alternatives to several industry standard amplifiers on the market today.
Typical Application - Voltage Controlled Oscillator (VCO)
0.05F
R VCC 100k 51k R/2 50k
-
1/2 CLCx050
+ V+/2 51k 51k
-
1/2 CLCx050
+ 100k
Output 1
Output 2 10k
Ordering Information
Part Number CLC1050IST5X CLC2050ISO8X CLC4050ISO14X Package SOT23-5 SOIC-8 SOIC-14 Pb-Free Yes Yes Yes RoHS Compliant Yes Yes Yes Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C Packaging Method Reel Reel Reel
Moisture sensitivity level for all parts is MSL-1.
Rev 1A
(c)2007-2009 CADEKA Microcircuits LLC
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Data Sheet
CLC1050 Pin Configuration
CLC1050 Pin Assignments
Pin No. 1 2 3 4 5 Pin Name OUT -VS +IN -IN +VS Description Output Negative supply Positive input Negative input Positive supply
OUT -V S +IN
1 2 3 +
5
+VS
4
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
-IN
CLC2050 Pin Configuration
CLC2050 Pin Configuration
Pin No. 1 Pin Name OUT1 -IN1 +IN1 -VS +IN2 -IN2 OUT2 +VS Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Negative supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Positive supply
OUT1 -IN1 +IN1 -V S
1 2 3 4
8 7 6 5
+VS OUT2 -IN2 +IN2
2 3 4 5 6 7 8
CLC4050 Pin Configuration
CLC4050 Pin Configuration
Pin No. 1 2 Pin Name OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2 OUT3 -IN3 +IN3 -VS +IN4 -IN4 OUT4 Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Positive supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Output, channel 3 Negative input, channel 3 Positive input, channel 3 Negative supply Positive input, channel 4 Negative input, channel 4 Output, channel 4
OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2
1 2 3 4 5 6 7
14 13 12 11 10 9 8
OUT4 -IN4 +IN4 -VS +IN3 -IN3 OUT3
3 4 5 6 7 8 9 10 11 12 13 14
Rev 1A
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Parameter Supply Voltage Differential Input Voltage Input Voltage Power Dissipation (TA = 25C) - SOIC-8 Power Dissipation (TA = 25C) - SOIC-14
Min 0 -0.3
Max 40 40 40 550 800
Unit V V V mW mW
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance SOT23-5 SOIC-8 SOIC-14
Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Min -65
Typ
Max 150 150 260
Unit C C C C/W C/W C/W
221 100 88
Recommended Operating Conditions
Parameter Operating Temperature Range Supply Voltage Range Min -40 3 (1.5) Typ Max +85 36 (18) Unit C V
Rev 1A
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3
Data Sheet
Electrical Characteristics
TA = 25C (if bold, TA = -40 to +85C), Vs = +5V, -Vs = GND, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions
G = +1, VOUT = 0.2Vpp, VS = 5V G = +1, VOUT = 0.2Vpp, VS = 30V G = +2, VOUT = 0.2Vpp, VS = 5V G = +1, VOUT = 0.2Vpp, VS = 30V G = +2, VOUT = 1Vpp, VS = 5V G = +2, VOUT = 2Vpp, VS = 30V VOUT = 1V step; (10% to 90%), VS = 5V VOUT = 2V step; (10% to 90%), VS = 30V VOUT = 0.2V step 1V step, VS = 5V 4V step, VS = 30V VOUT = 2Vpp, f = 1kHz, G = 20dB, CL = 100pF, VS = 30V > 10kHz, VS = 5V > 10kHz, VS = 30V Channel-to-channel, 1kHz to 20kHz
Min
Typ
330 550 300 422 107 76 4 5.6 1 200 285
Max
Units
Frequency Domain Response
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
UGBWSS BWSS BWLS
Unity Gain Bandwidth -3dB Bandwidth Large Signal Bandwidth
kHz kHz kHz kHz kHz kHz s s % V/ms V/ms
Time Domain Response
tR, tF OS SR Rise and Fall Time Overshoot Slew Rate
Distortion/Noise Response
THD en XTALK Total Harmonic Distortion Input Voltage Noise Crosstalk 0.015 45 40 120 2 7 VCM = 0V VCM = 0V DC, VS = 5V to 30V +VS = 15V, RL = 2k, VOUT = 1V to 11V RL = , VS = 30V RL = , VS = 5V RL = , VS = 30V RL = , VS = 5V RL = , VS = 30V RL = , VS = 5V 70 60 85 80 0.65 0.45 0.7 0.5 1.0 0.7 1.5 1.0 2.0 1.2 3.0 1.2 +VS - 1.5 70 100 20 5 100 100 200 30 100 5 7 % nV/Hz nV/Hz dB mV mV V/C nA nA nA nA dB dB dB dB mA mA mA mA mA mA
DC Performance
VIO dVIO Ib IOS PSRR AOL Input Offset Voltage (1) Average Drift Input Bias Current (1) Input Offset Current (1) Power Supply Rejection Ratio (1) Open-Loop Gain (1) Supply Current, CLC1050 (1) IS Supply Current, CLC2050 (1) Supply Current, CLC4050 (1) VOUT = 1.4V, RS = 0, VS = 5V to 30V
Input Characteristics
CMIR CMRR Common Mode Input Range (1,3) Common Mode Rejection Ratio (1) +VS = 30V DC, VCM = 0V to (+VS - 1.5V) 0 60 60 26 26 27 27
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V dB dB V V
Output Characteristics
+VS = 30V, RL = 2k VOH Output Voltage Swing, High (1) +VS = 30V, RL = 10k
28
V V
Rev 1A
(c)2007-2009 CADEKA Microcircuits LLC
4
Data Sheet
Electrical Characteristics continued
TA = 25C (if bold, TA = -40 to +85C), Vs = +5V, -Vs = GND, Rf = Rg =2k, RL = 2k to VS/2, G = 2; unless otherwise noted.
Symbol
VOL ISOURCE
Parameter
Output Voltage Swing, Low (1) Output Current, Sourcing (1)
Conditions
+VS = 5V, RL = 10k VIN+ = 1V, VIN- = 0V, +VS = 15V, VOUT = 2V VIN+ = 0V, VIN- = 1V, +VS = 15V, VOUT = 2V VIN+ = 0V, VIN- = 1V, +VS = 15V, VOUT = 0.2V
Min
Typ
5
Max
20 30
Units
mV mV mA mA A
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
20 20 10 5 12
40 15 50 40 60
ISINK ISC
Notes:
Output Current, Sinking
(1)
Short Circuit Output Current (1)
+VS = 15V
mA
1. 100% tested at 25C. (Limits over the full temperature range are guaranteed by design.) 2. The input common mode voltage of either input signal voltage should be kept > 0.3V at 25C. The upper end of the common-mode voltage range is +VS - 1.5V at 25C, but either or both inputs can go to +36V without damages, independent of the magnitude of VS.
Rev 1A
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Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = 30V, -Vs = GND, Rf = Rg =2k, RL = 2k, G = 2; unless otherwise noted. Non-Inverting Frequency Response
5 0 G=1 Rf = 0
Inverting Frequency Response
5 0
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
G = -1
Normalized Gain (dB)
-5 -10 -15 -20 -25 0.01 0.1 1
Normalized Gain (dB)
G=2 G=5
-5 -10 -15 -20 -25
G = -2 G = -5
G = 10
G = -10
VOUT = 0.2Vpp
VOUT = 0.2Vpp
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL
5 0 CL = 1nF Rs = 0 CL = 100pF Rs = 0
Frequency Response vs. RL
5 0
Normalized Gain (dB)
-5 -10 -15 -20
CL = 10nF Rs = 0 CL = 5nF Rs = 0
Normalized Gain (dB)
-5 -10 -15 -20
RL = 1K RL = 2K RL = 5K RL = 10K
VOUT = 0.2Vpp -25 0.01 0.1 1 10 -25
VOUT = 0.2Vpp
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT
5 0 -5 Vout = 4Vpp -10 -15 -20 -25 0.01 0.1 1 10
-3dB Bandwidth vs. VOUT
500
-3dB Bandwidth (KHz)
Normalized Gain (dB)
Vout = 2Vpp
400
300
200
100
0 0.0 1.0 2.0 3.0 4.0
Frequency (MHz)
VOUT (VPP)
Rev 1A
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Data Sheet
Typical Performance Characteristics
TA = 25C, +Vs = 30V, -Vs = GND, Rf = Rg =2k, RL = 2k, G = 2; unless otherwise noted. Non-Inverting Frequency Response at VS = 5V
5 0 G=1 Rf = 0
Inverting Frequency Response at VS = 5V
5 0
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
G = -1 G = -2 G = -5
Normalized Gain (dB)
-5 -10 -15 -20 -25 0.01 0.1 1
Normalized Gain (dB)
G=2 G=5
-5 -10 -15 -20 -25
G = 10
G = -10
VOUT = 0.2Vpp
VOUT = 0.2Vpp
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL at VS = 5V
5 0 CL = 1nF Rs = 0 CL = 100pF Rs = 0
Frequency Response vs. RL at VS = 5V
5 0
Normalized Gain (dB)
-5 -10 -15 -20
CL = 10nF Rs = 0 CL = 5nF Rs = 0
Normalized Gain (dB)
-5 -10 -15 -20
RL = 1K RL = 2K RL = 5K RL = 10K
VOUT = 0.2Vpp -25 0.01 0.1 1 10 -25
VOUT = 0.2Vpp
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT at VS = 5V
5 0 Vout = 1Vpp -5 Vout = 2Vpp -10 -15 -20 -25 0.01 0.1 1 10
-3dB Bandwidth vs. VOUT at VS = 5V
400 350
-3dB Bandwidth (KHz)
Normalized Gain (dB)
300 250 200 150 100 50 0 0.0 0.5 1.0 1.5 2.0
Frequency (MHz)
VOUT (VPP)
Rev 1A
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, +Vs = 30V, -Vs = GND, Rf = Rg =2k, RL = 2k, G = 2; unless otherwise noted. Small Signal Pulse Response
2.65 2.60
Large Signal Pulse Response
5.00
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
4.00
Output Voltage (V)
2.55 2.50 2.45 2.40 2.35 0 10 20 30 40 50
Output Voltage (V)
3.00
2.00
1.00
0.00 0 10 20 30 40 50
Time (us)
Time (us)
Small Signal Pulse Response at VS = 5V
2.65 2.60
Large Signal Pulse Response at VS = 5V
4.00 3.50
Output Voltage (V)
2.55 2.50 2.45 2.40 2.35 0 10 20 30 40 50
Output Voltage (V)
3.00 2.50 2.00 1.50 1.00 0 10 20 30 40 50
Time (us)
Time (us)
Supply Current vs. Supply Voltage
1 0.9 0.8 CLC4050
Input Voltage Range vs. Power Supply
15
Supply Current (mA)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 VOUT = 0.2Vpp
Input Voltage (+/-Vdc)
10 NEGATIVE POSITIVE
CLC2050 CLC1050
5
15
20
25
30
35
40
0 0 5 10 15
Supply Voltage (V)
Power Supply Voltage (+/-Vdc)
Rev 1A
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8
Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, +Vs = 30V, -Vs = GND, Rf = Rg =2k, RL = 2k, G = 2; unless otherwise noted. Voltage Gain vs. Supply Voltage
120 RL=2K 105
Input Current vs. Temperature
20 18 16
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Input Current (nA)
32 40
Voltage Gain (dB)
14 12 10 8 6 4
90
RL=20K
75 VOUT = 0.2Vpp 60 0 8 16 24
2 0 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V)
Temperature (C)
Functional Block Diagram
VCC
6A
4A
100A Q5 Q6
Q2 - Inputs Q1
Q3 Q4
Cc
Q7 Rsc Output
+ Q10 Q8 Q9
Q11 Q12 50A
Q13
Rev 1A
(c)2007-2009 CADEKA Microcircuits LLC
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9
Data Sheet
Application Information
Basic Operation Figures 1, 2, and 3 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
+Vs 6.8F
Power Dissipation Power dissipation should not be a factor when operating under the stated 2k ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply x IRMS supply
Output
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Input
+ -
0.1F Output 0.1F RL Rf
G = 1 + (Rf/Rg)
Rg -Vs
6.8F
Figure 1. Typical Non-Inverting Gain Circuit
+Vs 6.8F
R1 Input Rg
+ -
0.1F
Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in figure 3 would be calculated as: RL || (Rf + Rg)
0.1F 6.8F -Vs
RL Rf
G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg
Figure 2. Typical Inverting Gain Circuit
+Vs 6.8F
Input
+ -
0.1F Output RL 0.1F 6.8F -Vs
These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using:
G=1
Figure 3. Unity Gain Circuit
Rev 1A
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Data Sheet
(VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available.
2.5 SOIC-16 2
CL (pF) 1nF 5nF 10nF 100
RS () 0 0 0 0
-3dB BW (kHz) 485 390 260
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
440
Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx050 will typically recover in less than 30ns from an overdrive condition. Figure 6 shows the CLC1050 in an overdriven condition.
4 3.5 4 3.5 3 Input
Maximum Power Dissipation (W)
1.5
SOT23-6
1
0.5
SOT23-5
0 -40 -20 0 20 40 60 80
Ambient Temperature (C)
Figure 4. Maximum Power Derating
VIN = 1.25Vpp G=5
Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 5.
Input + Rf Rg Rs CL RL
Input Voltage (V)
3 2.5 2 1.5 1 0.5 0 -0.5 Output
Output Voltage (V)
2.5 2 1.5 1 0.5 0 -0.5
Output
0
20
40
60
80
100
Time (us)
Figure 6. Overdrive Recovery
Figure 5. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB peaking in the frequency response. The Frequency Response vs. CL plot, on page 6, illustrates the response of the CLCx050.
(c)2007-2009 CADEKA Microcircuits LLC www.cadeka.com
Rev 1A
11
Data Sheet
Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CaDeKa has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # CEB002 CEB006 CEB018 CLC1050 CLC2050 CLC4050 Products Figure 7. CEB002 Schematic
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 7-14. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 8. CEB002 Top View
Rev 1A
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Data Sheet
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Figure 9. CEB002 Bottom View
Figure 11. CEB006 Top View
Figure 12. CEB006 Bottom View
Figure 10. CEB006 Schematic
Rev 1A
(c)2007-2009 CADEKA Microcircuits LLC
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13
Data Sheet
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
Figure 14 CEB018 Top View
Figure 13. CEB018 Schematic
Figure 15. CEB018 Bottom View
Typical Applications
R1
Opto Isolator R6
-
1/2 CLCx050
VCC
AC Line
SMPS
+
GND
Battery Pack R7
R3 Current Sense R2
R4
R5
- VCC
1/2 CLCx050
+
AZ431
GND
R8
Rev 1A
Figure 16. Battery Charger
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14
Data Sheet
Vcc
R1 R2 100K R3 91K 910K
1/2 CLCx050
-
VCC
+ 2V -
R3 2k
+ 2V - - 1/2 CLCx050 + I1
R1 2k
R2
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
+VIN
+ RL
VO
I2
R4 3k
1mA
Figure 17. Power Amplifier Figure 20. Fixed Current Sources
+V1
R1 100k R2 100k R3 100k R4 100k R3 100k R4 100k R6 100k R5 100k
+
R1
VO
+V2
1/2 CLCx050
-
1M R2 0.001F 100k
-
+V3
+V4
1/2 CLCx050
+
VO
Vcc
R5 100k
Figure 18. DC Summing Amplifier
Figure 21. Pulse Generator
R1 C1 0.1F 100k - CIN R3 1M
R2 1M CO RB 6.2k R4 100k VCC AV = 1 + R2/R1 AV = 11 (As shown) VO
0
1/2 CLCx050
+
C1 0.01F VO RL 10k VIN R1 16k R2 16k C2 0.01F
+
AC
1/2 CLCx050
-
VO R3 100k R4 100k
C2 10F
R5 100k
fO
fO=1kHz Q=1 AV=2
Figure 19. AC-Coupled Non-Inverting Amplifier Figure 22. DC-Coupled Low-Pass Active Filter
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Rev 1A
15
Data Sheet
Mechanical Dimensions
SOT23-5 Package
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
SOIC-8 Package
Rev 1A
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16
Data Sheet
Mechanical Dimensions continued
SOIC-14 Package
Comlinear CLC1050, CLC2050, CLC4050 Low Power, 3V to 36V, Single, Dual, Quad Amplifiers
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2007-2009 by CADEKA Microcircuits LLC. All rights reserved.
Rev 1A
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